Electrically programmable array logic (EPALs) use a plurality of FAMOS transistors having gates coupled to input signals and source/drain region coupled between a product line and ground to implement logic functions. Sense amplifiers, which detect logic levels on the product line, may pull the product line to a voltage which will result in preventing premature FAMOS data gain. Previously developed sense amplifiers use a stacked transistor design to achieve the required pull-up. The operating point of the two transistors moves along the edge of the linear and saturated region, thus operating like a resistive pull-up. The current supplied by the stacked transistor pull-up will therefore be dependent upon the voltage of the product line. The higher the product line voltage, the lower the current supplied. When the product line's voltage approaches the clamp voltage, the current diminishes greatly. This effect may be great enough to skew the output transitions, making the low-to-high transitions slower than the high-to-low transitions, even though the FAMOS cell will sink increasing current with the decreasing product line voltage when it is pulling the line low.
The stacked transistor design must also be highly intolerant to process variations. If the N-channel transistors are weakened through any kind of parameters changes, such as VTO, BE (body effects), or KP, the performance of the sense amplifier will be greatly altered. The trip point of the CMOS inverter sense amplifier will also be skewed with process variations which can work against the slowest transition, and may even cause threshold problems.
Other sense amplifiers utilize a resistor divider type of pull-up to achieve the low voltage "high" required to prevent premature FAMOS data gain. In this design, a reference voltage tracks with process variations to control N-channel and P-channel fluctuations.
The low-to-high transition of such sense amplifiers is sacrificed by the pull-down resistor divider. The higher the product line voltage, the more the pull-up current is channeled from the product line capacitance to the pull-down transistor, which helps to slow down the low-to-high transition. The high-to-low transition creates a situation where the FAMOS cell pulling the line low must sink increasing current with decreasing product line voltage. This sense amplifier operation sacrifices the high-to-low transition speed.
Therefore, a need has arisen to provide a high-speed process tolerate sense amplifier providing a low voltage cutoff to eliminate premature FAMOS data gain.